This invention relates to test structures used in the fabrication of semiconductor integrated circuits, and more particularly, to test structures used to measure metal bottom coverage in semiconductor integrated circuits and a method for creating such test structures.
Test structures are known in the art and are commonly used in the manufacture of semiconductor integrated circuits. Various types of test structures are used in the semiconductor industry in an effort to improve process precision, accuracy and to simplify manufacturing of an integrated circuit wafer. Test structures are also employed to help shrink the sizes of integrated circuits and the size of individual electrical elements within integrated circuits. They are also used in an effort to help improve and increase the processing speed of these devices.
One problem commonly encountered in the manufacture of integrated circuits is measuring the amount of metal deposited during the manufacturing process. Specifically, metal may be deposited at the bottom or lower level of a trench structure, or a contact or via structure, that is created during the manufacture of the integrated circuit. These trenches, vias and contacts are typically created by etching through a particular layer previously deposited during the manufacturing process. Metal and other materials are then deposited within these trenches, vias and/or contacts in order to establish electrical contact between different layers of the semiconductor sandwich.
In order to monitor and improve the manufacture of integrated circuits, it may be important to measure the thickness or amount of metal deposited in the bottoms of these etched structures. The conventional way to measure bottom coverage is to cross section a sample integrated circuit wafer and take Scanning Electron Microscope (SEM) or Transmission Electron Microscope (TEM) micrographs. Sample preparation for SEM and TEM is tedious and performing wafer maps with these techniques is impractical. This process is also time consuming and by nature destructive of the particular integrated circuit tested.
Other known test structures used in the manufacture of integrated circuits include conventional Kelvin structures and line resistance structures. These other techniques, however, cannot successfully be used to measure metal coverage in the bottom of trenches, vias and/or contacts. In addition, the current qualification method used to measure film deposition uniformity is to create a 4-point probe wafer map of deposited metal over a flat wafer. However, unlike measuring surface uniformity across the wafer surface, bottom coverage uniformity may be unrelated to top surface uniformity, and the area of greatest concern in semiconductor manufacturing is the amount of material deposited at the bottom of topography features.
What is lacking in the art is a test structure for measuring the amount of metal deposited in the bottom of etched structures quickly. The property of Titanium Silicide reacting and having high etch selectivity as compared to Ti alone could be used to pattern such structures. With such a non-invasive technique for measuring metal coverage, automated tests may be performed to measure metal bottom coverage unlike the previously known cross sectioning techniques. As a result, many more integrated circuits can be monitored and/or tested during manufacture in order to improve device yield and other operating parameters.
In view of the above, a test structure for measuring metal bottom coverage, and a method for creating the test structure, is provided. According to the method of the invention, a layer of undoped material is deposited according to a predetermined test structure over a first isolation layer. A second isolation layer is deposited over the undoped material. The second isolation layer is then etched in a predetermined manner. A layer of metal is deposited over the exposed areas of the undoped material. Heat is then applied to the metal layer. A current is next applied to the predetermined test pattern, and the electrical resistance of the test pattern is measured.
According to the test structure of the invention, a plurality of probe contacts are deposited on a layer of undoped material according to a predetermined test pattern. At least one area of exposed undoped material is disposed between a first and a second probe contact. A metal layer is deposited over the at least one exposed area of undoped material. A layer of reacted metal and undoped material is disposed at the at least one exposed area of undoped material.
Through the electronic measurement of metal bottom coverage, many wafer samples may be measured quickly and repeatedly. Unlike SEM or TEM cross sectional analysis, wafer maps may be easily produced and used for in-line measurements and equipment qualification. Moreover, electrical measurements have the ability to be repeated unlike the previously known cross sectioning tests. The step coverage of metals at the bottom of a trench structure may also be more easily assessed. The invention also improves the precision and accuracy, and simplifies, the manufacturing of integrated circuits.
These and other features and advantages of the invention will become apparent upon a review of the following detailed description of the presently preferred embodiments of the invention, taken in conjunction with the appended drawings.